Semantic Caching Framework: An FPGA-Based Application for IoT Security Monitoring

Security monitoring is one subdomain of cybersecurity which aims to guarantee the safety of systems, continuously monitoring unusual events. The development of Internet Of Things leads to huge amounts of information, being heterogeneous and requiring to be efficiently managed. Cloud Computing provides software and hardware resources for large scale data management. However, performances for sequences of on-line queries on long term historical data may be not compatible with the emergency security monitoring. This work aims to address this problem by proposing a semantic caching framework and its application to acceleration hardware with FPGA for fast- and accurate-enough logs processing for various data stores and execution engines

MASCARA (ModulAr Semantic CAching fRAmework) towards FPGA Acceleration for IoT Security Monitoring

With the explosive growth of the Internet Of Things (IOTs), emergency security monitoring becomes essential to efficiently manage an enormous amount of information from heterogeneous systems. In concern of increasing the performance for the sequence of online queries on long-term historical data, query caching with semantic organization, called Semantic Query Caching or Semantic Caching (SC), can play a vital role. SC is implemented mostly in software perspective without providing a generic description of modules or cache services in the given context. Hardware acceleration with FPGA opens new research directions to achieve better performance for SC. Hence, our work aims to propose a flexible, adaptable, and tunable ModulAr Semantic CAching fRAmework (MASCARA) towards FPGA acceleration for fast and accurate massive logs processing applications

Mozaïc : plate-forme générique de modélisation et de conception d'architectures reconfigurables dynamiquement

Constant evolution of applications and an ever increasing need for performances make necessary the use of new dynamically reconfigurable systems on chip every times more highly capable and scalable. Consequently, these architectures constantly grow in complexity in terms of reconfiguration process and conception. The major issue was to design development frameworks based on high level architecture description languages (ADL). The ADLs are useful for the fast specification of hardware implementation and useful for giving architecture informations to the front-end tools. The area of this thesis is the architecture description, computer-aided design (CAD) and exploration of dynamically reconfigurable architectures. This document presents the development framework Mozaïc which aims at designing dynamically reconfigurable architecture by automatic generation of hardware resources needed. In the first part of this document, we detail the dynamic reconfiguration concepts developed and used by Mozaïc. In the second part, we present the ADL xMAML which permits the description and the efficient exploration of the concepts presented in the first part. This ADL is based on the MAML language developed at the University of Erlangen in Germany, to which was extended by adding new parameters required to make feasible dynamic reconfiguration of heterogeneous computing units. The last part of the document is dedicated to the presentation of the framework itself and of the various tools used to develop two reconfigurable architectures: FPGA and the DART. In particular is included the dynamic reconfiguration exploration and implementation of a WCDMA receiver on both architectures.L'évolution constante des applications et le besoin toujours croissant de performances imposent le développement de nouvelles architectures compétitives et évolutives au sein de systèmes reconfigurables dynamiquement sur puces. Ces contraintes ont amené à une complexification des architectures, de leurs mécanismes de reconfiguration et de leur conception. De manière à répondre efficacement à ce problème, des plate-formes de développement ont été conçues et permettent ainsi d'automatiser certains processus constituant la chaîne de conception d'une architecture. Cela est rendu possible par l'intermédiaire d'un langage de description haut niveau (ADL) qui permet, par une spécification rapide de certains paramètres matériels, de procéder rapidement à la génération d'une architecture et de ses outils de développement adaptés tels que des outils de simulation, de compilation ou encore de synthèse. Cette thèse se place dans le contexte de la modélisation haut niveau des architectures ainsi que dans le contexte de l'aide à la conception et à l'exploration d'architectures reconfigurables dynamiquement. Ce document présente la plate-forme de développement Mozaïc dont l'objectif est de permettre la conception d'architectures reconfigurables dynamiquement par l'introduction automatique de ressources matérielles dédiées et adaptées. Dans une première partie, nous détaillons les concepts de reconfiguration dynamique qui ont été développés et mis en oeuvre dans Mozaïc. Dans une deuxième partie, nous présentons le langage de description haut niveau xMAML qui permet la spécification de l'architecture et de l'exploitation efficace des mécanismes précédemment présentés. Ce langage est basé sur l'ADL MAML développé à l'université d'Erlangen, auquel nous avons ajouté certains paramètres de spécifications nécessaires à la mise en oeuvre de la reconfiguration dynamique ainsi qu'à la spécification d'architectures hétérogènes. Enfin, dans un dernier chapitre, nous présentons les différentes phases de développement, et les outils associés, de deux architectures reconfigurables dynamiquement que sont les FPGAs et le processeur reconfigurable DART. Cette présentation inclut les phases d'exploration et l'implémentation d'un décodeur WCDMA par reconfiguration dynamique sur le FPGA modélisé par xMAML

Semantic caching framework, an application to FPGA-based application for IoT security monitoring

International audienceSecurity monitoring is one subdomain of cybersecurity which aims to guarantee the safety of systems, continuously monitoring unusual events. The development of Internet Of Things leads to huge amounts of information, being heterogeneous and requiring to be efficiently managed. Cloud Computing provides software and hardware resources for large scale data management. However, performances for sequences of on-line queries on long term historical data may be not compatible with the emergency security monitoring. This work aims to address this problem by proposing a semantic caching framework and its application to acceleration hardware with FPGA for fast-and accurate-enough logs processing for various data stores and execution engines

Mozaïc (plate-forme générique de modélisation et de conception d architectures reconfigurables dynamiquement )

Cette thèse se place dans le contexte de la modélisation haut niveau des architectures ainsi que dans le contexte de l'aide à la conception et à l'exploration d'architectures reconfigurables dynamiquement. Ce document présente la plate-forme de développement Mozaïc dont l'objectif est de permettre la conception d'architectures reconfigurables dynamiquement par l'introduction automatique de ressources matérielles dédiées et adaptées. Nous présentons également le langage de description haut niveau xMAML qui permet la spécification de l'architecture et de l'exploitation efficace des mécanismes précédemment présentés. Enfin, la dernière partie de ce document s'attache à présenter l'utilisation de la plate-forme Mozaïc et plus particulièrement les différentes phases de développement d'un décodeur WCDMA implémenté par reconfiguration dynamique sur deux architectures reconfigurables dynamiquement que sont les FPGA et le processeur reconfigurable DART.This thesis attempts to define an architectural description language for computer-aided design conception and exploration of dynamically reconfigurable architectures. This document presents the development framework Mozaïc which aims at designing dynamically reconfigurable architecture by automatic generation of the required hardware resources. In the first part of this document, we detail the dynamic reconfiguration concepts developed and used by Mozaïc. In a second part, we present the ADL xMAML which allows the description and the efficient exploration of the concepts presented in the first part. Parameters specific to dynamic reconfiguration have been added in ADL which is based on the MAML language. The last part of the document is dedicated to the presentation of the framework itself and especially on the dynamically reconfigurable implementation of a WCDMA decoder on both a FPGA architecture and on the DART architecture.RENNES1-BU Sciences Philo (352382102) / SudocSudocFranceF

xMAML: a Modeling Language for Dynamically Reconfigurable Architectures

International audienceConstant evolution of norms and applications, usually implemented on system-on-chip (SOC), increases ar- chitecture performance and flexibility requirements. Current architectures are consequently becoming more complex and difficult to develop. One of the solutions is to develop design frameworks based on high-level architecture description languages (ADL). These ADLs are useful for a rapid description of the hardware that should be implemented on an architecture. Designers can use ADL for the development of generic front- end tools. Our framework aims at designing dynamically reconfigurable architecture with the help of an ADL. This paper presents xMAML, an architecture description language dedicated to the instantiation of dynamically reconfigurable heterogeneous computing units. From this ADL, a synthesizable model is produced after exploration, simulation and validation phases. As proof of concept, exploration for a WCDMA receiver on two dynamically reconfigurable architectures is presented

Efficient Dynamic Reconfiguration for Multi-context Embedded FPGA

International audienceDynamic reconfiguration on fine-grained architecture can only be reached by multi-context FPGAs when reconfiguration time is a critical issue. Un- fortunately the multiple contexts bring power and area overhead. This pa- per introduces the Dynamic Unifier and reConfigurable blocK (DUCK), a new structure to perform efficiently dynamic reconfiguration. The DUCK allows to separate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process using the DUCK concept is presented in detail and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA receiver on a multi-context embedded FPGA and demonstrates the interest and the efficiency of using dynamic reconfiguration

Plate-forme de Conception d'Architectures Reconfigurables Dynamiquement pour le Domaine du TSI

International audienc

Efficient and Flexible Dynamic Reconfiguration for Multi-Context Architectures

International audienceDynamic reconfiguration is possible on both fine-grain and coarse-grain architectures. One of the used methodology used consists in the use of multi-context architectures. Unfortunately, the multi- ple contexts bring power and area overhead. This paper introduces the Dynamic Unifier and reConfigurable blocK (DUCK) concept, a new structure to perform efficiently dynamic reconfigura- tion on both custom designed fine-grain and coarse grain architectures. The DUCK allows to sepa- rate the configuration path and the configuration registers which facilitates simultaneous configuration and computing steps. The reconfiguration process is presented in detail, and synthesis results are given for different structures. Our solution is finally validated with the implementation of a WCDMA (Wideband Code Division Multiple Access) receiver on a multi-context embedded FPGA and on the dynamically reconfigurable processor DART. This implementation demonstrates the inter- est and the efficiency of the use of dynamic reconfiguration and the proposed flexible structure